A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture

A stochastic ADC is naturally a non-uniform non-linear quantizer, in which post-correction is typically needed. In addition, even though it can achieve high precision, the range of a stochastic ADC is limited. Therefore, it is beneficial to use the stochastic array as a fine-stage in a sub-ranging architecture. In this work,look-up-table linearization with full mapping and sigma-based mapping for a stochastic ADC and sub-ranging stochastic ADC are examined and compared experimentally by Monte Carlo simulation and measurement. A test chip is fabricated for 4-bit coarse flash stage and 127 comparator arrays on 0.18 μm CMOS. Measurements confirmed simulation results, and it is shown that full mapping can improve equivalent number of bit by 2 bits compared to sigma-based mapping. Furthermore, the results suggest that the coarse stage comparator with 5 times better input offset variation than fine stage comparator is suitable for sub-ranging implementation.