Extending a CPU Cache for Efficient IPv6 Lookup

Increasing throughput requirements for Internet routers and growing routing table sizes have emphasized the need for fast and scalable packet forwarding systems. This paper presents a hardware cache-based IPv6 lookup system. Our goal is to study how much performance can be achieved with a lookup system that is implemented by modifying a processor cache. We show by prototyping our system on an FPGA board that our solution provides efficient IPv6 packet forwarding. In particular, the solution’s hardware complexity grows only linearly with table size. Our basic FPGA implementation can support a 1Gb link for minimum sized packets, and an improved implementation, discussed in this paper, could improve this throughput by an order of magnitude. Finally, an ASIC implementation would support 100Gb of bandwidth if there is no other bottleneck in the system.