On the use of Probabilistic Parallel Bit-Flipping decoder for the storage systems

The soft-decision Low-Density Parity-Check (LDPC) decoders have been applied in several storage systems thanks to their powerful error correction capability. However, these systems may suffer a long read latency since the soft-decision decoders require an intensive computations as well as a long sensing time for the soft-information before decoding. In this paper, we modify the recent-introduced Probabilistic Parallel Bit-Flipping (PPBF) LDPC decoder, to use on the storage systems in replacing the soft decision decoders, to improve the memory reading speed. The modified decoder is named Non-Syndrome Probabilistic Parallel Bit-Flipping (NS-PPBF). A special flipping mechanism is introduced such that the decoder can stop flipping without requiring the syndrome check results, which helps significantly improve the decoding frequency. We provide also the hardware architecture to implement NS-PPBF on the LDPC code used on the memory systems, which are usually very long block length with very high rate. The advantages of using NS-PPBF decoder in terms of error correction and decoding throughput are confirmed by the simulating decoding performance and the hardware synthesis.