Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs

With the dramatic increase in utilization of FPGAs to accelerate compute/data intensive applications on embedded platforms, providing customized/optimized multi-ported memory architectures for FPGAs are of paramount importance. FPGAs achieve high speedup by exploiting parallelism in computations, which requires multi-ported memories to provide any number of ports for simultaneous and multiple read/write (R/W) operations. Most of the existing multi-ported memory designs become complex due to the extra logic and routing required to provide an arbitrary number of R/W ports. In this paper, we introduce four unique, novel, and optimized counter-based multi-ported memory architectures. With our memories, circular paths are eliminated; thus significantly reducing the design/routing complexity, while enhancing the operating frequency and area-efficiency. As a result, our memories can be seamlessly integrated to the existing and next-generation FPGAs. Our proposed memories are evaluated with the most recent multi-ported memory designs in the literature.