A −194 dBc/Hz FoM VCO with Low-Supply Sensitivity for Ultra-Low-Power Atomic Clock

This paper presents a high performance CMOS VCO with specific design features required for chip scale atomic clock(CSAC). The CMOS architecture with noise filtering at the current source enables the VCO to achieve low power with good phase noise performance for the targeted application. Additional PVT frequency compensation is realized to mitigate the power supply induced frequency modulation. The VCO has been implemented in a standard 65 nm CMOS process for validation. It achieves phase noise of -120 dBc/Hz at 1MHz offset frequency while consuming only 0.89 mW with a flat frequency stability around nominal supply voltage.