Supply Noise Induced Jitter Reduction in Package Power Distributed Networks for 28 Gbps High Speed Serial Links

This paper presents an IC package co-design methodology to reduce power supply noise induced jitter for 28 Gbps high speed serial link in tsmc 28nm technology with 10-layers FCBGA substrate. To reduce the supply noise induced jitter, the package design is enhanced at the power distributed networks (PDNs) in layout design phase. The enhancements are reduction at power supply parasitic inductance and isolation at cross-power domains. Through the proposed methodology, the supply noise induced jitter is reduced 800% at the output eye-diagram of 28 Gbps high speed serial link, compared with the design without PDNs enhancement, and also without package manufacturing cost increment.