3D Crosspoint Memory as a Parallel Architecture for Computing Network Reachability

A novel in-memory computing design that can compute single-source reachability and transitive closure of graphs is introduced. The proposed design leverages the parallel flow of information in three-dimensional crosspoint memories and can be implemented using memories with two layers of 1-diode 1-resistor (1D1R) interconnects. Our logic-in-memory designs mitigate the infamous memory-processor bottleneck characteristic of John von Neumann architectures and have runtime complexities of O(n) and O(n
²
) using O(n
²
) memory cells for the single-source reachability and transitive closure problems, respectively, where n is the number of nodes in the graph. This work builds upon preliminary results presented in [1].