Interconnect Trend for Single Digit Nodes

Transistor performance continues to improve with density scaling and move to FinFET architectures. However, feature size reduction increases parasitic contact and interconnect resistance. This degrades the power-performance equation. To address the resistance bottleneck; new materials, new fill technologies and new integration schemes are in play. This paper reviews metallization trends for contact and interconnect as the industry prepares for 7nm node production and looks towards developing 5 and 3nm nodes.