Selective Fin Trimming after Dummy Gate Removal as the Local Fin Width Scaling Approach for N5 and Beyond

Selective fin trimming after dummy gate removal is proposed as the local fin width scaling approach for further FinFET extension. In this approach, local fin trimming is selectively performed for the channel region after dummy gate removal in the replacement metal gate (RMG) module while preserving the original source and drain (S/D) fin width, in order to avoid the parasitic resistance increase that results from the global fin trimming approach. TCAD simulation shows clearly that the local fin trimming can improve gate electrostatics with narrower fins, while also providing the benefits of lower S/D resistance and PMOS high channel stress. Although, fin height reduction and parasitic capacitance increases are not preferable, overall gate delay is improved due to strong
$I_{\text{on}}-I_{\text{off}}$
boost. Selectra™ etch fin trimming results are also presented demonstrating good fin width controllability and smaller variations without any critical fin damages. This local fin trimming is promising for N5 and beyond to further extend FinFET technology.