Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits

The advantages of CMOS differential-stack current-mode logic techniques together with the load-driving capability, switching speed, and noise immunity of bipolar devices has been exploited to develop a novel enhanced folded source coupled logic (FSCL) technique. A pair of quiet low-impedance push-pull load steering emitter followers (EF's) are implemented at the mutually complementary outputs of the CMOS FSCL (CFSCL) gate to obtain the EF/sup 2/SCL gate structure. This modification considerably improves the performance of the gate at low supply voltages for a mixed-mode environment (e.g., /spl Sigma//spl Delta/ data converters in digital audio, video, and radio frequency applications) without the cost of substantial power-supply spikes. Thorough current steering and dynamic-charge storage analysis at 100 MHz, using a 3.3-V supply voltage and BSIM process parameters was performed to evaluate the performance enhancement achievable by the EF/sup 2/SCL technique. A 4-bit carry-lookahead with carry skip was achieved in 2 ns using a single EF/sup 2/SCL logic gate, compared to 9 ns for a CFSCL gate. In addition, the deterioration of the voltage-swing (and hence the noise margin) with power-supply scaling and increased differential logic input stack-size is considerably more pronounced in a CFSCL gate compared to an EF/sup 2/SCL gate. EF/sup 2/SCL thus permits logic implementation using fewer stages compared to CFSCL, and hence reduces delay latency in a pipelined system. A tiny chip using MOSIS Orbit 2-/spl mu/m n-well analog CMOS process (which provides a p-base diffusion layer for low-cost n-p-n device option) was used for the experimental verification.