New Worst-Case Timing for Standard Cells Under Aging Effects

The design of reliable circuits in current semiconductor technologies requires worst-case estimations of degradation effects during chip signoff. Hence, semiconductor vendors provide worst-case cell delays in the form of slow/slow process corners and best-case cell delays in fast/fast process corners. By providing these corner cases, EDA signoff tools can accurately estimate the circuit timing in which a reliable operation (i.e., no timing violations) is guaranteed for the projected lifetime. State of the art assumes that a standard cell exhibits the worst-case delay increase when all of its transistors uniformly exhibit worst-case aging-induced degradation. As our first contribution, we are the first to demonstrate that this assumption is incorrect and leads to a considerable underestimation of up to 55% in circuit timing. To find the worst-case cell delay, instead of searching across all combinations of non-uniform transistor degradations, we propose reducing the search space by exploiting circuit topology, that is, using cell input vectors to determine transistor duty cycles. Our aim is to find the worst-case input vectors of a cell, which lead to the highest possible shift in rise and fall propagation delay for each standard cell. Since the number of inputs of a standard cell is significantly smaller than its number of transistors, exploring this reduced search space becomes feasible. We show how considering a uniform worst-case degradation for each transistor underestimates the actual degradation in standard cells. In fact, actual non-uniform worst-case inputs vectors result in 83% higher standard cell delay on average (compared to applying peak degradation uniformly) with a peak of $60\boldsymbol \times $ for an inverter under a high load capacitance.