Adding Support for Nanomips Architecture to QEMU Emulator

While developing new microprocessor architectures, availability of emulations of such architectures even before their physical production is of great significance. Adding support for a recently concieved and designed architecture - nanoMIPS - to emulator QEMU is presented in this paper. The main steps needed for successful QEMU emulation of nanoMIPS base instruction set architecture are presented. In addition, the implementation of an innovative organization of MIPS-specific QEMU segments that allows easier integration of future MIPS architectures in QEMU is described.