Drafting in Self-Timed Circuits

Intervals between data items propagating in self-timed circuits are controlled by handshake signals rather than by a clock. In many self-timed designs, a trailing data item will catch up with a leading item or token, even when it trails by thousands of gate delays. This effect, called “drafting,” can be seen in many of the self-timed designs, e.g., GasP, Mousetrap, Click, and Micropipeline. Drafting occurs because the delay of a trailing token through a self-timed stage depends on how much earlier the leading token departed. Contrary to earlier work, we find the cause of drafting to be charge stored on an isolated node between two series transistors. This mechanism occurs in many decision gates that implement a logical AND. The charge on the floating internal node can drift between actions and thereby change the delay of the gate. Drafting behavior may be modulated by controlling the internal node of the GasP NOR gate. This offers possibilities for using self-timed circuits in applications where the interval between data items carries information, for instance, spiking neural networks, security, or real-time signal processing.