A 0.65-V 10-bit 320-kS/s SAR-ADC with Charge Average and Skip Switching Algorithm

A high resolution and low power fully differential 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this work aiming at neural signal data acquisition. By utilizing surplus energy restored by MSB-split capacitors of alternative switching structure both in conversion phase and reset phase, the proposed charge average and skip switching algorithm achieves superior DAC switching energy efficiency without the requirement of an external Vcm reference. Implemented in 180nm CMOS process, the proposed chip occupied a 0.0564-mm
²
core area. Operating at 320-kS/s sampling rate with 0.65-V supply voltage, it achieved an ENOB of 9.66-bit and FoM of 6.26 fJ/conv.-step. The measured DNL and INL results are within 0.29 LSB and 0.38 LSB, respectively.