A Chip-Area-Efficient Subthreshold CMOS Voltage Reference with High PSRR Based on Compensated ΔVGS of NMOS Transistors

A chip-area-efficient subthreshold CMOS voltage reference (CVR) with low power consumption and high power supply ripple rejection (PSRR) based on compensated ΔV
_GS
of NMOS transistors is proposed in this paper. The ΔV
_GS
of two different-V
_th
NMOS transistors is designed to achieve zero temperature coefficient (TC) by compensating its complementary -to-absolute-temperature (CTAT) and proportional-to-absolute- temperature (PTAT) components. An error amplifier driving a current mirror is then used to duplicate the generated zero-TC ΔV
_GS
to a diode-connected NMOS and provide the low-TC V
_REF
. Only two branches are needed in the core part and no resistors are used. Consequently, low power and small area consumptions are achieved with high PSRR. A prototype design is fabricated in a standard 0.18-μm CMOS process. An average TC of 27.26 ppm/°C is measured across 6 dies with a standard derivation of 16.40 ppm/°C over -40 to 80 °C temperature range. The measured line sensitivity is 0.12%/V. The measured PSRR is better than -62.7dB from 10 kHz to 10 MHz. The power consumption is as small as 17.3nW and the chip area is only 0.0244mm
²
.