Effect of Vds Variation on the Trapped Charge Distribution of a SONOS Memory

In this paper, simulation of SONOS memory cell has been performed. We investigate the effect of various Vds values in order to observe the charge distribution in the floating gate. By varying drain voltage from 0 to 5 V and maintaining gate voltage constant at 8 volt, we observed a decreasing programming threshold voltage. I-V curve shows threshold voltage shifts according to the variation of voltage drain. Furthermore, we also observed a spatial distribution of trapped electrons in floating gate which is changing as the voltage drain is varied.