VLSI Components with Fault Mitigation Design. RTL Model and Synthesis

The fault mitigation for modern embedded systems developed by thin design rules (40 nm and less) is necessary feature due to accelerating aging and manufacturing defects, for which diagnosis during the chip testing at fabric is impossible. One of the most used methods to provide fault mitigation is spatial redundancy. Main parameter to measure strength of mitigation is probability to fail, or mean time between failures (MTBF). One of the important and critical parameters in VLSI is area. Area is a hardware cost of spatial redundancy. To implement VLSI with necessary parameters of fault mitigation and area some approaches may be used during hardware description and its synthesis. In addition, some important point need to be taken in account. This article considers these approaches and points.