Advanced Multiplier Design and Implementation using Hancarlson Adder

Finite Impulse Response (FIR) filters, microprocessors and digital signal processors are the core system of multipliers. The Multiplier and Accumulator Unit (MAC) is the predominant block in a Digital Signal Processing (DSP) system. The objective of MAC is implementation of signal processing with high performance but multiplier most of the time occupies much area and become power consuming circuits. In this paper, a Modified Russian Peasant Multiplier (MRPM) using Hancarlson adder (HA) has been proposed. According to Russian Rules, a Divide and conquer technique is used in the multiplication process. But, in the perspective of digital design, only shifters and adders are used in the Russian Peasant Multiplier (RPM) to produce a Partial Product Generation (PPG). In this paper, we present an approach towards the reduction of delay in existing RPM by using HA, in the partial product reduction stage and proposed RPM with HA at Partial Product Addition (PPA). The proposed design is also compared to the RPM with Ripple Carry Adder (RCA), Carry Selector Adder (CSA) and 8-2 Adder Compressors (AC) in terms of propagation delay. The proposed design enhances speed of the system by 80.4% compared to the RPM using RCA, 81.7% compared to RPM using CSA and 77.5% compare to RPM with 8:2 adder compressors (AC's). The total operation is coded with Verilog Hardware Description language (HDL) using Model-Sim 6.3C, synthesized by using the Xilinx Integrated Software Environment (ISE) 14.7 design tool.