Design of A CML Driver Circuit in 28 nm CMOS Process

CML driver circuit is an essential part of high-speed serial interfaces. This paper presents a low-voltage high-speed CML driver circuit at 1.05V supply voltage in UMC 28nm CMOS process. The design adopts four levels cascade main driver circuit and pre-emphasis circuit. The pre-emphasis circuit include emphasis circuit and adjust the emphasis range circuit. Designed and verified in Cadence IC615, the proposed circuit's output swing is 500mV, the bit rate can reach 12.5Gbps, the power consumption is 28.9mW, emphasis can achieve 11.48 dB.