An 8-Bit High Speed Successive Approximation Analog-to-Digital Converter

In this paper, an 8-Bit 51 MS/s SAR-ADC in 180 nm CMOS Process is designed. This SAR-ADC utilizes a high-speed clocked-comparator to improve the comparing speed. The converter adopts an improved DAC structure to eliminate the negative influence brought by the large unit capacitance (16fF) that limits the speed of SAR-ADC. The simulation results show that the SNDR of the ADC is 44.3 dB, the SFDR is 51.6dB, and the ENOB is 7.07dB at 25 MHz input signal frequency and 51MHz sample clock frequency. The total power dissipation of this converter is 0.61mW, and the FOM is 89fj/conv with a 1.8V supply. Based on the large capacitance under standard process, the design in this paper doubles the speed compared to the original structure with only one more register and 0.05mW more power consumption.