Design of High Speed Dynamic Comparator in 28nm CMOS

This paper presents a high-speed dynamic comparator which could optimize the basically differential amplifier and class AB latch circuit, designed and verified in UMC 28nm CMOS process with Cadence IC615. The proposed design is powered by 1.05V supply and the output signal only exhibits 0.2mV/0.8mV offset voltage, 63ps/44ps delay respectively when the clock signal at the 5/10 GHz. The proposed circuit is useful for the electronic industries, high-speed ADCs and SerDes.