Efficient Architecture for Implementation of Hermite Interpolation on FPGA

Interpolation is widely used for a number of applications. For instance, it is used to generate geometric models, path trajectories and various applications of signal processing including data compression. Traditionally, software implementation of interpolation is carried out using a General Purpose Processor (GPP) or Digital Signal Processor (DSP). Field Programmable Gate Arrays (FPGAs) however, offer a more customizable and faster solution. This paper presents a hardware accelerator architecture for Hermite Interpolation on FPGA. Cubic Hermite interpolation, specifically Catmull-Rom spline is preferred over other techniques due to ease of computation and local control which makes it an ideal method to implement very low-complexity architecture. A data flow approach has been used as it provides high throughput for intensive data processing. Additionally, the efficiency of computation has been improved by implementing a pipelined architecture. The proposed architecture has been implemented on Xilinx Zynq-7000 AP SoC XC7Z020-CLG484 using the Xilinx Vivado Design Suite. Results obtained from fixed point FPGA implementation were found to have high fidelity with floating point MATLAB simulations. Root Mean Squared Error (RMSE) of 1.704×10
^-4
and a correlation of 99.84% was obtained.