Optimization of Full-Chip Power Distribution Networks in 3D ICs

In this paper, we propose a method to minimize resources of power distribution networks (PDNs) in a three-dimensional integrated circuit (3D IC) under the given design constraints. We first present modeling of PDNs with RC reduction. Next, we describe the optimization of PDN parameters using a multi-objective optimization algorithm. The decoupling capacitors, on-chip power/ground grids, and power/ground through-silicon vias (TSVs), which have a great influence on the voltage drop (IR drop) and on the chip area increase, are optimized. The experimental results demonstrate that the new proposed method is effective for designing PDNs in 3D ICs.