Heterogeneous Routing: A Methodology for PPA Tradeoff in Network-On-Chips

This paper proposes a routing algorithm design methodology based on real network traffic analysis. The method aims at large-scaled network on chip in which load differs among different areas or routing nodes. By applying different routing algorithms on different nodes, the area and/or power consumption can be saved only at the cost of minor performance loss. Experimental results show that by replacing routing nodes using NoP routing algorithm with nodes using XY routing algorithm, up to 10% of routing nodes can be simplified into much less power/area costing nodes, saving at least 2 % of area overhead, only at the cost of 5% of performance loss.