All-Digital Delta-Sigma TDC with Differential Multipath Pre-Skewed Gated Delay Line Time Integrator

This paper presents an all-digital 1st-order 1-bit delta-sigma time-to-digital converter ( ΔΣ TDC) with a differential multipath pre-skewed bi-directional gated delay line (BDGDL) time integrator. Differential time integration is obtained by performing simultaneous left-shift and right-shift operations of the BDGDL. Pre-skewing is used to lower the per-stage delay and skew error of BDGDL. The time integrator features low power consumption accredited to the use of only one BDGDL to perform differential time integration, rapid time integration, full compatibility with technology, and built-in digitization. The TDC was designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. A sinusoidal time input of 333 ps amplitude and 244 kHz frequency is digitized by the TDC. Simulation results show the TDC provides 39.7 dB SNDR, 6.5 ENOB, and 3.7 ps time resolution over frequency range from flicker noise corner frequency 32 kHz to 3rd harmonic frequency 732 kHz while consuming 407 μW. The FOM of the TDC is 3.2 Pj/step, outperforming that of reported TDCs alike.