Calibration Mechanism for Input/Output Termination Resistance in 28nm CMOS

This paper presents a method of receiver and transmitter input/output resistance calibration in UMC 28nm CMOS process. Designed and verified in Cadence IC615, the actual calibration resistance of the simulation (approximately 200Ω, which is four times the impedance of the transmission line) with high robustness under all PVT conditions, and the maximum deviation is 0.85%. The proposed calibration mechanism can be applied to high-speed interface circuits such as LVDS, LVPECL, CML, etc.