A efficient placement and global routing algorithm for hierarchical FPGAs

In this paper an efficient placement and global routing algorithm for the hierarchical FPGAs (HFPGAs) is developed. This algorithm is based on a modified k-way min-cut technique which recursively partitions a cluster in k sub-clusters to facilitate the architecture of the HFPGAs. Through this algorithm, both the placement and global routing can be done simultaneously. The results of on a set of MCNC benchmark circuits show that the proposed algorithm is very efficient.