An FPGA-Based Divider Circuit Using Simulated Annealing Algorithm

Division is considered as the slowest and most difficult operation among four basic operations in microprocessors. This paper proposes a unique division algorithm using a new approach of simulated annealing algorithm. A heuristic function is proposed to determine the global and local optimum value, whereas the conventional approaches use random values to reach the target value. In addition, a new temperature schedule is introduced for faster computation of global maxima/minima. The proposed simulated annealing performs better than the best known existing method of simulated annealing algorithm for smooth energy landscape due to the introduction of a new goal-based temperature. Thus, the proposed division algorithm computes the current partial remainder and quotient bits simultaneously per iteration which reduces the delay of the proposed divider circuit significantly. Moreover, the proposed divider circuit requires only two operations per iteration, whereas the exiting best one requires three operations per iteration. The proposed divider circuit is coded in VHDL and implemented in a Virtex-6 platform targeting XC6VLX75T Xilinx FPGA with a -3 speed grade by using ISE 13.1. The proposed divider circuit achieves an improvement of 36.17% and 44.67% respectively in terms of LUTs and delay factor for a 256 by 128 bit division over the best known contemporary FPGA-based divider circuit. It can be used into the designs of arithmetic logic unit, image processing and robotics system. The experimental result indicates that the divider takes fewer resources, and its performance is steady and reliable.