The Merged Clock Gating Architecture For Low Power Digital Clock Application On FPGA

We propose a novel merged clock gating architecture to design low power digital clock which groups all clock gating signals together into a single clock gating signal, then uses one DEMUX gate to process and split the single clock gating signal into many different clocks. We compare the proposed technique with the conventional clock gating technique and no-clock gating technique in term of clock power, dynamic power and total power consumption. The simulation results in Spartan-3E shows total consumption power that the proposed architecture can save 3.45%, 26.53%, 50.69%, 53.15%, 53.13% compared to the no-clock gating and 1.19%, 1.85%, 11.83%, 14.76%, 15.67% compared to the conventional clock gating technique in operation frequency of 100MHz, 1GHz, 10GHz, 100GHz and 1THz, respectively. Moreover, the proposed technique can reduce to 20.88% and 5.28% compared to the no-clock gating and the conventional clock gating in term of the created operation temperature, respectively. The number of LUTs also decreases to 175 instead of 179 in the other clock gating techniques.