Automatic Topology Generation of 21 Bit Chipless Radio Frequency Identification Tags Using a Noniterative Technique

A design technique is proposed for the topology generation of chipless radio frequency identification (RFID) tags. When the capacity of chipless RFID is as high as 21 bits, the chipless tag consists of numerous closely spaced resonators, and mutual coupling incurs increasing numbers of design variables. Thus, synthesizing the resonant frequencies requires iterative simulations that fine-tune the design variables. As millions of items need to be mapped, the design of the high-capacity system is time-consuming. In this letter, a design methodology that does not need iterative optimization procedures is presented. This feature is implemented through three mechanisms. First, the half-wave slot is determined as the resonator for the tag. This resonator depicts the advantage of narrowband and harmonic rejection, yet it is simple in geometry. Second, the mutual coupling between the resonators is reduced through isolated ground planes. Third, a response surface model is formulated, and the resonant frequencies can be synthesized using the model without performing additional simulation. The proposed technique is verified through simulation and measurement. Thirty-five samples are transformed into the tag topologies. The results indicate that a reliability of 100% is achieved for these samples.