A Low Power CORDIC-Based Hardware Implementation of Izhikevich Neuron Model

In this paper, an efficient CORDIC-based hardware implementation of the Izhikevich neuron model is introduced. The CORDIC (COordinate Rotation Digital Computer) algorithm is used to approximate the square term in Izhikevich equations that describe the neuron response. The approximation is evaluated by defining four types of errors where the CORDIC approximation shows significant improvement in error performance compared to the Piecewise Linear (PWL) model [1]. The power consumption of the CORDIC-based neuron hardware implementation ranges from 0.26 mW to 0.4 mW whereas the PWL-based neuron as well as the original Izhikevich neuron hardware implementations consume 0.3 mW and 1.06 mW, respectively. A Figure of Merit (FoM) is defined to show the tradeoff among errors, power and area. By comparing with the PWL-based neuron hardware implementation, it is found that the CORDIC-based model is preferred as an approximation method from the error, power and area perspective.