A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation

A selectively activated 8× time-domain interpolation is proposed for a low-power high-speed 6-bit flash ADC. By improving the linearity of the voltage-to-time conversion gain, a 3-bit resolution is achieved in time-to-digital conversion. Hence, the number of the dynamic comparators is reduced from conventional 63 to 10. Also, unlike other time-domain interpolation schemes, time-to-digital converters are selectively activated to reduce the power consumption of the time-to-digital conversion. The flash ADC fabricated in a 1-V 65-nm CMOS process achieves 6 GS/s with 15.1-mW power consumption. It shows a 31.18-dB SNDR and an 85 fJ/conv.-step FoM with a Nyquist frequency input.