Multi-Channel FPGA Acquisition System for SDR Receivers

In this work, a based in FPGA acquisition system destined to Software Defined Radio (SDR) receivers is presented. The design includes a LEON3 embedded microprocessor which use the operative system RTEMS to execute the tasks that control the acquisition system and the communication interfaces. The system can be used in multiantenna receivers due to it allows acquiring samples from multiple inputs. A Direct Memory Access (DMA) interface over AMBA bus transfers the data to the RAM memory without the intervention of the processor. On the other hand, a client software, which runs in a PC, was developed to control, monitor and download the acquired samples. The design was tested using a Global Position System (GPS) receiver and the results obtained were satisfactory.