Design of a 2–12-GHz Bidirectional Distributed Amplifier in a 0.18- $\mu$ m CMOS Technology

This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18-μm CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages (nopt), maximum achievable power gain (GP), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., n) is offered where dc-power consumption of the circuit (Pdc) is also considered. This formula optimizes GP/Pdc, and it is preferred over the conventional nopt formula. To validate the theoretical analyses, a 2-12-GHz BDDA with high output 1-dB compression point of +16 dBm and small-signal gain of 10 dB is fabricated. The BDDA chip occupies 1.89-mm
²
die area, and its average measured noise figure and Pdc are 6.8 dB and 0.38 W in the high-power mode and 6.5 dB and 0.13 W in the low-power mode, respectively.