Three-Parallel Reed-Solomon Decoder using a Simplified Step-by-Step Algorithm

In this paper, the simplified step-by-step Reed-Solomon (RS) decoding algorithm was adopted in this work to reduce the hardware complexity and power consumption. According to the advantages of the step-by-step RS decoding algorithm, we propose the three-parallel hardware architecture to speed up the RS decoding rate without the need for recursively solving the error-location polynomial and performing the Forney algorithm. Finally, using TSMC 90nm technology, the proposed design has a working frequency of up to 286MHz. The gate counts and throughput of this chip core are approximately 131K gates and 6.8Gb/s at 286MHz, respectively.