Dual-mode Channel Decoding Kernel Design Using FBA-based Layered LDPC Decoding

This paper presents a dual-mode low-density parity-check (LDPC) and turbo decoding kernel for powerline communication systems. Because the layered decoding schedule achieves a fast convergence speed, the proposed dual-mode decoding kernel implements the forward-backward algorithm with the layered decoding schedule. A multifunction a posteriori calculator, one key module of the dual-mode decoding kernel, is proposed to achieve high hardware sharing in this paper. Thus, the proposed dual-mode decoding kernel can achieve efficient hardware usage.