A 1.4 V 10-bit 20 MSPS pipelined A/D converter

A 1.4 V 10-bit 20 MSPS pipelined analog-to-digital converter was implemented using 0.25 /spl mu/m CMOS technology. The converter is based on low-voltage two-stage opamps and current reference generator for low-voltage operation. The current reference generator adopts a newly proposed dual-mode voltage booster that keeps the reference current constant regardless of temperature and voltage variations under the low-voltage environment. The ADC occupies a die area of 2.21 mm/sup 2/ (1700 /spl mu/m/spl times/1300 /spl mu/m) and dissipates 43 mW and 20 MHz clock rate with a 1.4 V single supply. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.59 LSB and /spl plusmn/0.68 LSB, respectively.