FPGA versus GPU for Speed-Limit-Sign Recognition

We implement a speed-limit-sign recognition task using a template-based approach on the FPGA using the Intel FPGA SDK for OpenCL. Then we evaluate its throughput, power consumption, accuracy, and development effort against a GPU implementation that is based on a system presented in our previous study. This paper also discusses implementation differences between the FPGA and GPU systems, provides a methodology for translating the GPU system to the FPGA system, and explains optimizations used in the FPGA version. While implementing the FPGA system, we build an efficient FFT engine for image processing on the FPGA which can be utilized by other developers to perform related tasks. In this paper, we also provide our insights on building the FPGA versus GPU system, which we hope can be useful for designing upcoming versions of FPGA-focused OpenCL development environments. We conclude that the FPGA implementation provides better power consumption for the same detection accuracy, while the GPU supports better programmer efficiency.