Characterization of Intrinsic Capacitances of Power Transistors Under High Current Conduction Based on Pulsed S-Parameter Measurements

This work presents a measurement technique to characterize the intrinsic capacitances of power transistors under high current conduction. By using a network analyzer, a curve tracer and custom high current bias-tees, the proposed setup extends the limited bias conditions of standard characterization techniques to the high current linear and saturation regions of a power transistor. A state-of-the-art SiC power MOSFET is used as DUT. It is found that the intrinsic capacitances C
_GS
and C
_GD
experience a strong non-linearity with bias voltages V
_GS
and V
_DS
in the linear and saturation region. These results can be used for precise switching losses prediction and for the extraction of accurate transistor models. The C
_GS
(V
_GS
, V
_DS
) and C
_GD
(V
_GS
, V
_DS
) measurement results are used to derive the gate charge characteristics of the DUT, showing good agreement with those extracted under identical switching conditions in a DPT.