A 0.9-pJ/bit 10-Gb/s Controlled Capacitor-Discharge 2-bit Pulsewidth Modulator in 45-nm SOI CMOS

A unique pulsewidth modulation (PWM) architecture is presented which works by controlling the discharge rate of a capacitor. The designed PWM modulator consists primarily of a 2-bit current-steering digital-to-analog converter (DAC) and a voltage-to-time converter (VTC). The VTC operates in two phases. The first phase requires the capacitor to be charged to the supply rail, while the second phase discharges the capacitor using the control voltage generated by the DAC. The rate of the capacitor discharge defines the width of the output PWM pulse. The proposed PWM modulator, implemented in 45-nm silicon-on-insulator CMOS, occupies an active silicon area of 30 × 120 μm
²
, achieves data rates upto 10 Gb/s and dissipates only 9 mW of total power. To the best of the authors' knowledge, the proposed PWM modulator achieves the best energy per bit figure and is the most power area efficient reported to date.