A 4.7-mW 12-bit 100-MS/s Hybrid DAC

This paper presents a 12-bit digital-to-analog converter (DAC) with hybrid structure combining the current steering with the R-2R ladder structure, which can be used in low power applications demanding less than 100 MS/s conversion speed. It provides more than 85 dB spurious free dynamic range (SFDR) with 1 MHz output signal at 100 MHz sampling clock frequency. The achieved differential non-linearity (DNL) and integral non-linearity (INL) are equal to 0.91 and 0.81 LSB, respectively. The hybrid converter design is based on 55 nm CMOS technology and the overall system consumes 4.71 mW from 1.2 V digital (0.67 mW) and 2.5 V (4.04 mW) analog power supplies.