(Invited) Recent insights in CMOS reliability characterization by the use of degradation maps

In modern VLSI devices, a multitude of degradation mechanisms dictates limits on the tolerable voltage conditions to guarantee reliable operation for extended times. The most critical degradation mechanisms such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD) are mostly studied in terms of their mean degradation. By obtaining large statistical datasets, covering a multitude of conditions in the {V
_G
,V
_D
} bias space, typically obtained by measurements on dedicated on-chip FET arrays, we show that we can identify the active degradation mechanisms and understand their impact on both FET time-zero metrics, as well as on the time-dependent variability.