A floating high voltage gate driver with latch function

This paper describes a gate driver with latch function to achieve low power consumption. The proposed scheme adopts a floating high voltage level shifter to solve the problem of the voltage resistance of the gate-source of the output PMOS. Furthermore, latches and feedback circuits are added to reduce the power consumption. Under the condition that load capacitance C
_L
is 15nF and the supply voltage V
_DDH
is 14V, simulation results indicate that the turn on delay time t
_d(on)
and turn off delay time t
_d(off)
of the gate driver is 619ns and 151ns, respectively. Moreover, the dead time of the gate driver is 28ns, and the gate driver consumes 6μA quiescent current at room temperature. The layout area of the gate driver is 900μm×600μm.