An SRAM-free HEVC Deblocking Filter VLSI Architecture for 8K Application

Deblocking filter (DBF) is an efficient tool to reduce the bit rate in the latest video coding standard, High Efficiency Video Coding (HEVC). This work presents an SRAM-free deblocking filter VLSI architecture with high throughput and efficiency. To avoid the usage of SRAM inside the DBF module, the basic filter unit (BFU) is designated as 8 × 8 block size and the vertical boundaries in 8 × 8 block will be filtered firstly followed by the horizontal. Besides, the block in & out and block filtering will be performed by pipeline to improve DBF throughput. Based on the proposed architecture, it takes 4 cycles to finish one BFU processing, one cycles for one boundary between two 4 × 4 blocks. The experimental result shows that our design can support 8K@120fps real-time video coding with TSMC 65nm process, which occupies 23.5K gates at 400NHz.