High Performance WSe2 Transistors with Multilayer Graphene Source/Drain

P-channel WSe
₂
FETs along with multilayer graphene source/drain (S/D) are demonstrated by the CVD growth of the WSe
₂
monolayer to the patterned graphene. Multilayer graphene (MLG) is adopted to reduce contact resistance while the monolayer WSe
₂
served as the channel for the electrostatics integrity of the FET. Furthermore, by increasing the p-type doping concentration of the graphene S/D, the I
_on
/I
_off
ratio can be enhanced to 10
⁸
and the unipolar p-channel characteristics are retained regardless the choice of the work function of the metal used for the S/D contact.