Performance Improvement of Delta-Sigma ADC/DAC/TDC Using Digital Technique

This paper reviews the authors' group research results of data-weighted averaging (DWA) algorithm for multi-bit ΔΣADC/DAC/TDC and also dithering techniques for ΔΣ ADC/DAC for limit cycle reduction. When a multi-bit internal DAC or digital-to-time converter (DTC) is used inside a modulator, nonlinearities of the DAC/DTC are not noise-shaped and the SNR of the ΔΣADC/DAC/TDC degrades. To overcome this problem, we investigate several algorithms to noise-shape the DAC/DTC nonlinearities. Also we investigate limit cycle suppression techniques in ΔΣDAC. Then we discuss their generalization.