A Novel Customized RC Tightened Corner Modeling Methodology Using Statistical SPICE Simulation in Advanced FinFET Technology

In this work, a novel RC tightened corner modeling methodology using statistical simulation is proposed for the advanced FinFET technology. Based on foundries' parasitic RC techfile, MEOL (Middle-End-Of- Line) and BEOL (Back-End-Of-Line) parasitic of customized layout is modeled from different PEX (Parasitic Extraction) corner data. The tightened corner range considers layer-cancellation is defined from benchmark circuit composed by customized layout. As a result, a customized RC tightened corner techfile is developed to satisfy various in-house pattern to avoid over-pessimistic or over-optimistic parasitic RC variation.