Chip-Level CDM Circuit Modeling and Simulation for ESD Protection Design in 28nm CMOS

Charged device model (CDM) ESD protection design is an emerging design challenge for ICs. Chip-level CDM ESD protection circuit simulation is extremely difficult due to its complexity including modeling. This paper presents a novel CDM modeling and circuit simulation method for chip-level CDM ESD protection circuit design verification and prediction, which was applied to ICs designed in a foundry 28nm CMOS technology.