Drift region engineering to reduce hot carrier effects on high voltage MOSFETs

In this paper, we discuss strategies to reduce hot carrier (HC) effects on two different high voltage MOSFET devices types. One type is an LDMOS device which is a lateral device, and the other type is a shielded gate trench power MOSFET (SGTM) which is a vertical device. These two device types are widely used for different high voltage applications such as switch-mode power supplies, power amplifiers and DC/DC power supplies. HC injection has significant effects on both device types' performance. For SGTM, we have found that the HC injection in the device's off-state can strongly affect BV
_DSS
(drain to source breakdown voltage) even at very short stress times (~100 seconds). This HC effect can be mitigated by adjusting the drift region doping concentration to compensate for the charge due to HC injection. For LDMOS, we develop a practical method to reduce the HC effect without sacrificing the Rdson or BV
_DSS
by increasing the oxide thickness over the drift region.