A fast variable-length decoder using plane separation

This paper has developed a fast variable-length decoder which uses a plane separation technique to reduce the processing time of the feedback path in the decoder. The developed decoder performs two shift processes and a decision process concurrently. Therefore, the processing time in the feedback path of our developed variable length decoder can be improved and determined by the longest time among the three processes, not by the sum of their processing times together. Our simulation results show that the total processing time of our developed decoder makes about 30% improvement from that of the Sun and Lei's (1991, 1992) decoder and their modified decoder when they are implemented with field programmable logic device.